Design Verification Engineer – First Silicon & IP

Apple Inc.; California; On-site; USD 175,000 - 309,000; Full time

Benefits offered by this job

Employee stock purchase plan

Comprehensive medical and dental

Retirement benefits

Job summary

Apple Inc. in California seeks an outstanding design verification engineer to enable the production of fully functional first silicon for IP designs.

You will own DV methodology, test-plan development, and verification environment creation, including stimulus and checkers, with coverage tracking. You will develop block, IP and SoC level test-benches, drive verification bring-up and regression, and report DV progress using diverse metrics.

Qualifications

• BS degree in a technical subject with proven experience.
• Deep knowledge of SystemVerilog and UVM required.
• Experience building scalable, portable verification environments.
• Familiarity with LLMs for verification efficiency is encouraged.

Responsibilities

• Study design specifications and create a test plan.
• Develop DV infrastructure in SystemVerilog/UVM to stress the design.
• Fix issues from regressions and close bugs.
• Use LLMs to improve verification efficiency and quality.

Skills

SystemVerilog

UVM

OOP

Test benches

verification methodologies

LLMs

Power-aware UPF

Python

PCIe

USB

Education

BS degree in technical subject area

Tools

Simulators

Waveform viewers

Build and run automation

Coverage tooling

Job description

Apple Inc. in California seeks an outstanding design verification engineer to enable the production of fully functional first silicon for IP designs.

You will own DV methodology, test-plan development, and verification environment creation, including stimulus and checkers, with coverage tracking. You will develop block, IP and SoC level test-benches, drive verification bring-up and regression, and report DV progress using diverse metrics.