ASIC Design Engineer

Lumicity; San Jose (CA); On-site; USD 100,000 - 150,000; Full time

Job summary

Lumicity, located on-site in San Jose, CA, is offering an exciting opportunity to work on high-speed digital integrated circuits. The successful candidate will engage in High-Speed Digital Design, RTL Design, and Synthesis for next-generation products. Required qualifications include a B.S. or M.S. in Electrical Engineering and extensive experience with Verilog or SystemVerilog, as well as EDA tools like Cadence and Synopsys. Ideal candidates will have a strong foundation in Digital ASIC Design and scripting experience with Python, TCL, or Perl.

Qualifications

• Experience working with Hardware Description Languages such as Verilog or SystemVerilog.
• Strong background in Digital ASIC Design understanding complete ASIC design flow.
• Must have worked with EDA tools like Cadence or Synopsys.

Responsibilities

• Work on High-Speed Digital Design and RTL Design.
• Participate in Clock Domain Crossing, Synthesis and Timing Closure.

Skills

Verilog

SystemVerilog

Digital ASIC Design

Cadence EDA tools

Synopsys EDA tools

Python

TCL

Perl

Education

B.S. or M.S. in Electrical Engineering

Tools

Tempus

PrimeTime

Genus

Design Compiler

Formality

JasperGold

Job description

Located on-site in San Jose, CA

Overview:

This is an exciting opportunity to work on high-speed digital integrated circuits for a startup who have a groundbreaking technology and have raised over $100million in funding. You will be working on High-Speed Digital Design, RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for the companies next generation products.

• B.S. or M.S. in Electrical Engineering, Computer Engineering or similar
• Experience working with Hardware Description Languages such as Verilog or SystemVerilog
• A strong background working on Digital ASIC Design with the understanding of complete ASIC design flow from specification to tape-out.
• Must have worked with Cadence or Synopsys Electronic Design Automation tools such as Tempus, PrimeTime, Genus, Design Compiler, Formality or JasperGold
• Scripting experience with either Python, TCL or Perl
• Experience working on Static Timing Analysis, Synopsys Timing Constraints, Clock Domain/Reset Domain

Preferred Skills (Not Essential):

• Working with protocols for Optical Communications
• Digital Data Communication techniques including scrambling or forward error correction (FEC)