Lead ASIC DFT Engineer – RTL, CDC & SVA

Cisco Systems; Seattle (WA); On-site; USD 187,000 - 268,000; Full time

Benefits offered by this job

Medical, dental & vision insurance

401(k) with company matching

Paid parental leave

Short and long-term disability

Life insurance

Job summary

Cisco Systems in Seattle area seeks an experienced ASIC Design Engineer to define, design, and verify ASIC subsystems across Cisco platforms. You will collaborate with a cross-functional team to meet power, performance, and area targets while documenting and developing ASIC subsystems for high-volume deployment.

The role emphasizes defining processes and tools for complex design implementations, with strong RTL, CDC/RDC expertise and gate-level optimization experience.

Qualifications

• Bachelor’s with 8+ years or related experience, or master’s with 6 + years of related experience, or PhD + 3 years of related experience
• Prior experience with RTL development skills and experiences
• Prior experience with CDC/RDC concepts and relevant design implementation
• Prior Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
• Prior experience with static glitch harzads and experience on the relevant analysis on synthesis optimized gate netlists

Responsibilities

• Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.

Skills

RTL development

CDC/RDC concepts

sign-off constraints

synthesis optimization

Education

Bachelor's degree + 8+ years

Master's + 6+ years

PhD + 3 years

Tools

VCS simulation

SystemVerilog Assertions (SVA)

Job description

Cisco Systems in Seattle area seeks an experienced ASIC Design Engineer to define, design, and verify ASIC subsystems across Cisco platforms. You will collaborate with a cross-functional team to meet power, performance, and area targets while documenting and developing ASIC subsystems for high-volume deployment.

The role emphasizes defining processes and tools for complex design implementations, with strong RTL, CDC/RDC expertise and gate-level optimization experience.