Lead ASIC DFT Emulation & Strategy

Cisco; San Jose (CA); On-site; USD 214,000 - 310,000; Full time

Job summary

Cisco is seeking an ASIC DFT - Emulation Technical Leader to define and drive the DFT emulation strategy for Silicon One. You will architect a greenfield pre-silicon emulation roadmap, build a high-performing team, and validate complex scan, MBIST and JTAG architectures on Palladium, Veloce and Zebu.

You will collaborate with RTL, physical design, ATPG and vendors to enable seamless silicon bring-up and push multi-terabit validation.

Qualifications

• Proficiency in Verilog and SystemVerilog is required.
• Experience with C/C++ and scripting languages (Tcl or Python/Perl) is required.
• Emulation experience on Palladium, Veloce, or Zebu and related compilation/debug skills are essential.

Responsibilities

• Define and drive the DFT emulation strategy for Silicon One.
• Lead the pre-silicon emulation roadmap and build a high-performing team.
• Validate complex scan, MBIST and JTAG architectures on major emulation platforms.
• Collaborate with RTL, physical design, ATPG teams and vendors to enable silicon bring-up.

Skills

Verilog/SystemVerilog

C/C++

Scripting (Tcl/Python/Perl)

Education

Bachelor's degree

Master's degree

PhD

Tools

Palladium

Veloce

Zebu

Job description

Cisco is seeking an ASIC DFT - Emulation Technical Leader to define and drive the DFT emulation strategy for Silicon One. You will architect a greenfield pre-silicon emulation roadmap, build a high-performing team, and validate complex scan, MBIST and JTAG architectures on Palladium, Veloce and Zebu.

You will collaborate with RTL, physical design, ATPG and vendors to enable seamless silicon bring-up and push multi-terabit validation.