Lead ASIC DFT engineer.

Accord Technologies Inc; San Jose (CA); On-site; USD 150,000 - 180,000; Full time

Job summary

Accord Technologies Inc is seeking a Lead ASIC DFT Engineer in San Jose, CA. This position involves architecting and implementing DFT solutions for complex ASIC and SoC designs. With a requirement of over 10 years of experience in DFT, the candidate must be proficient in scan architecture, JTAG, ATPG, and silicon debug. The work setup is remote with monthly in-office meetings. Strong knowledge of Synopsys, Cadence, and other EDA tools is preferred, along with scripting experience in TCL, PERL, or Python.

Qualifications

• 10+ years of hands-on experience in ASIC Design-for-Test (DFT).
• Experience leading cross-functional debug efforts.
• Proven expertise in silicon bring-up.

Responsibilities

• Architect, implement, verify, and debug advanced DFT solutions.
• Lead technical ownership across DFT architecture.
• Drive resolution of critical silicon issues.

Skills

ASIC DFT experience

Scan architecture

ATPG

MBIST

JTAG

Boundary scan

Silicon debug

Python scripting

Tools

Synopsys

Cadence

Siemens/Mentor EDA tools

Job description

Overview

Role: Lead ASIC DFT Engineer

Location: San Jose, CA

Work Setup: Remote however once/month in office. PST time zone preferred

Designation: Associate

Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

Key Skills Required

• Strong hands-on ASIC DFT experience with end-to-end ownership
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
• Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
• Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
• MBIST implementation and verification; SMS experience preferred
• Tessent/SSN experience preferred
• Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
• Post-silicon debug and silicon bring-up experience
• TCL, PERL, or Python scripting experience is highly preferred