Lead ASIC DFT Architect - Remote

CAONE; United States; On-site; USD 150,000 - 230,000; Full time

Job summary

CAONE seeks a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation.

The ideal candidate will lead cross-functional debugging efforts and drive robustness, quality and yield, while mentoring junior engineers and evaluating emerging DFT methodologies.

Qualifications

• Hands-on ownership of DFT for ASIC/SoC designs.
• Strong understanding of fault models and test coverage concepts.
• Experience with scan insertion, ATPG, MBIST/LBIST, and JTAG.

Responsibilities

• Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
• Drive scan architecture, insertion, stitching, and compression for high coverage.
• Own MBIST/LBIST integration across design and silicon bring-up.
• Perform DFT debugging, failure analysis, root-cause investigation, and fault coverage closure.
• Develop and validate DFT constraints including DFT SDC and timing checks.
• Collaborate with RTL, verification, physical design, STA, and silicon validation teams.
• Support ATPG pattern generation, ATPG simulations, DRC, and test coverage analysis.
• Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
• Review RTL/ synthesis/ LEC impacts on DFT implementation and test quality.
• Mentor junior and mid-level DFT engineers; promote best practices.
• Develop TCL/Python scripts to improve flow efficiency and debugging productivity.

Skills

End-to-end DFT

Scan architecture

ATPG

MBIST/LBIST

JTAG/boundary scan

DFT debugging

RTL Synthesis

Scripting TCL/PERL

Timing analysis

DFT fault models

Cross-functional leadership

SoC/ASIC design

Tools

Synopsys

Cadence

Mentor Graphics

Tessent

iJTAG

Job description

CAONE seeks a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation.

The ideal candidate will lead cross-functional debugging efforts and drive robustness, quality and yield, while mentoring junior engineers and evaluating emerging DFT methodologies.