ASIC DFT Emulation Strategy Lead

Cisco Systems, Inc.; San Jose (CA); On-site; USD 214,000 - 310,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) with Cisco matching

Paid parental leave

Paid time off

Job summary

Cisco Systems, Inc. is seeking an ASIC DFT - Emulation Technical Leader to own the pre-silicon emulation roadmap for Silicon One.

You will architect a greenfield strategy, build a capable team, and set the standards for validating MBIST, JTAG, and scan architectures on Palladium, Veloce, and Zebu. You will work closely with RTL, physical design, and ATPG teams to push multi-terabit validation and drive silicon bring-up.

Qualifications

• Bachelors + 12 years of related experience, or Masters + 8 years, or PhD + 5 years of related experience.
• Prior emulation experience on Palladium, Veloce, or Zebu with compilation and debugging.
• Proficiency in Verilog and SystemVerilog.
• Proficiency in C/C++ and scripting (Tcl or Python/Perl).

Responsibilities

• Define and drive the DFT emulation strategy for Silicon One’s DFT team.
• Lead and build a high-performing emulation engineering team.
• Collaborate with RTL, physical design, and ATPG teams to bring up silicon and validate complex architectures.

Skills

DFT emulation

Verilog/SystemVerilog

Education

Bachelor's degree in related field

Master's degree in related field

PhD in related field

Tools

Palladium

Veloce

Zebu

C/C++

Tcl/Python/Perl scripting

Job description

Cisco Systems, Inc. is seeking an ASIC DFT - Emulation Technical Leader to own the pre-silicon emulation roadmap for Silicon One.

You will architect a greenfield strategy, build a capable team, and set the standards for validating MBIST, JTAG, and scan architectures on Palladium, Veloce, and Zebu. You will work closely with RTL, physical design, and ATPG teams to push multi-terabit validation and drive silicon bring-up.