Senior ASIC DFT Lead: Post-Silicon & Test Strategy

Cisco; San Jose (CA); On-site; USD 214,000 - 310,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) plan with company match

Paid parental leave

Job summary

Cisco Silicon One team seeks an ASIC Technical Lead in San Jose to drive Design-for-Test and quality across the ASIC flow. You will align front-end RTL with backend physical design, shaping DFT requirements early and guiding post-silicon validation activities.

Ideal candidates bring 12+ years in ASIC/DFT, strong debugging skills, and hands-on experience with JTAG, ATPG, and industry tools like Tessent and PrimeTime.

Qualifications

• BS/MS in Electrical or Computer Engineering with 12+ years in ASIC/DFT roles.
• Experience with post-silicon debugging from first silicon to production.
• Hands-on with JTAG, Scan, and memory BIST architectures.

Responsibilities

• Lead DFT and quality processes across the implementation flow.
• Collaborate with Front-end RTL and backend physical design teams.
• Drive DFT requirements early in the design cycle.
• Contribute to post-silicon validation and sign-off activities.

Skills

DFT leadership

JTAG protocols

ATPG / BIST architectures

Gate level debugging

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

TestMax

Tetramax

Tessent

PrimeTime

VCS

Job description

Cisco Silicon One team seeks an ASIC Technical Lead in San Jose to drive Design-for-Test and quality across the ASIC flow. You will align front-end RTL with backend physical design, shaping DFT requirements early and guiding post-silicon validation activities.

Ideal candidates bring 12+ years in ASIC/DFT, strong debugging skills, and hands-on experience with JTAG, ATPG, and industry tools like Tessent and PrimeTime.