Emulation Technical Lead - ASIC DFT Champion

Cisco Systems

San Jose (CA)

On-site

USD 214,000 - 310,000

Full time

11 days ago
Application generator

Get a reply from this employer — a resume and cover letter tailored to exactly what they’re hiring for.

Get past ATS filters

Job summary

Cisco Systems in San Jose is seeking an ASIC DFT - Emulation Technical Leader to own the DFT emulation strategy for Silicon One. You will architect the pre-silicon emulation roadmap, build a high-performing team, and define validation flows for scan, MBIST, and JTAG on Palladium, Veloce, and Zebu.

You will collaborate with RTL, physical design, ATPG teams and vendors to enable seamless silicon bring-up and push multi-terabit validation, shaping Cisco's next-gen silicon platforms.

Qualifications

  • Bachelor's + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience.
  • Prior emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation and debug.
  • Prior experience with Verilog and System Verilog.
  • Prior experience with C/C++ and scripting skills with Tcl or Python/Perl.

Responsibilities

  • Own and define the DFT emulation strategy for Silicon One and lead the emulation roadmap from scratch.
  • Architect pre-silicon emulation flows and validate complex scan, MBIST, and JTAG architectures on Palladium, Veloce, and Zebu.
  • Collaborate with RTL, physical design, ATPG teams, and vendors to enable seamless silicon bring-up and multi-terabit validation.

Skills

Verilog
SystemVerilog
C/C++
Scripting Tcl/Python/Perl

Education

Bachelor's degree (or higher) in related field

Tools

Palladium
Veloce
Zebu

Job description

Cisco Systems in San Jose is seeking an ASIC DFT - Emulation Technical Leader to own the DFT emulation strategy for Silicon One. You will architect the pre-silicon emulation roadmap, build a high-performing team, and define validation flows for scan, MBIST, and JTAG on Palladium, Veloce, and Zebu.

You will collaborate with RTL, physical design, ATPG teams and vendors to enable seamless silicon bring-up and push multi-terabit validation, shaping Cisco's next-gen silicon platforms.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Emulation & DFT Strategy Lead for ASIC Silicon One
Emulation & DFT Strategy Lead for ASIC Silicon One

020 Cisco Systems, Inc. • San Jose (CA)

On-site
USD 214,000 - 310,000
ASIC DFT Emulation Strategy Lead
ASIC DFT Emulation Strategy Lead

Cisco Systems, Inc. • San Jose (CA)

On-site
USD 214,000 - 310,000
Medical, dental, and vision insurance
401(k) with Cisco matching
Paid parental leave
+1
Lead ASIC DFT Emulation & Strategy
Lead ASIC DFT Emulation & Strategy

Cisco • San Jose (CA)

On-site
USD 214,000 - 310,000
Senior ASIC DFT Lead: Post-Silicon & Test Strategy
Senior ASIC DFT Lead: Post-Silicon & Test Strategy

Cisco • San Jose (CA)

On-site
USD 214,000 - 310,000
Medical, dental and vision insurance
401(k) plan with company match
Paid parental leave
Innovative ASIC DFT Engineer - Design for Test
Innovative ASIC DFT Engineer - Design for Test

Cisco Systems, Inc. • San Jose (CA)

On-site
USD 120,000 - 190,000
Health insurance
401(k) matching
Paid parental leave
+2
ASIC DFT Engineer
ASIC DFT Engineer

Cisco Systems, Inc. • San Jose (CA)

On-site
USD 120,000 - 150,000
Senior ASIC Architect: High-Performance Mixed-Signal & DFT
Senior ASIC Architect: High-Performance Mixed-Signal & DFT

020 Cisco Systems, Inc. • Carlsbad (CA)

On-site
USD 192,000 - 276,000
Medical, dental and vision insurance
401(k) with Cisco matching
Paid parental leave
+1
ASIC Emulation Engineer — HW/SW Co-Verification Lead
ASIC Emulation Engineer — HW/SW Co-Verification Lead

Advanced Micro Devices • Santa Clara (CA)

On-site
USD 160,000 - 230,000
DFT Engineer - ASIC Test & Automation Specialist
DFT Engineer - ASIC Test & Automation Specialist

Anysilicon • San Jose (CA), Northern (KY)

Hybrid
USD 120,000 - 150,000
DFT Engineering Lead for ASIC Test & Debug
DFT Engineering Lead for ASIC Test & Debug

Broadcom Inc. • San Jose (CA)

On-site
USD 144,000 - 230,000
Medical, dental and vision plans
401(K) with company match
Employee Stock Purchase Program (ESPP)
+4