Senior ASIC Architect: High-Performance Mixed-Signal & DFT

020 Cisco Systems, Inc.

Carlsbad (CA)

On-site

USD 192,000 - 276,000

Full time

4 days ago
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Benefits offered by this job

Medical, dental and vision insurance
401(k) with Cisco matching
Paid parental leave
Cisco restricted stock units (RSUs)

Job summary

Cisco Systems, Inc. in California seeks a technical leader to define and productize high-performance mixed-signal ASICs and DFT frameworks.

You will own architecture for blocks and subsystems, partnering with domain experts to solve cross-functional challenges and lead scalable verification strategies across digital and analog domains. You will also drive reusable designs, automation flows, and engage with tool vendors and IP suppliers, collaborating with library, PnR, Test Eng, and Operations

Qualifications

  • Bachelor’s degree with 12+ years relevant experience, or Master’s with 8+ years, or PhD with 5+ years.
  • Ownership of DFT architecture development for an SoC is preferred.
  • Experience implementing at-speed scan, MBIST, BISR and boundary-scan techniques.

Responsibilities

  • Define architecture and productize high-performance mixed-signal ASICs and DFT frameworks.
  • Own blocks/subsystems architecture, collaborating with domain experts to solve cross-functional challenges.
  • Lead project-level design and scalable verification strategies for high-speed digital and analog blocks.
  • Develop reusable designs and automated flows/scripts for the team.
  • Lead engagements with tool vendors and IP suppliers and collaborate across library, PnR, Test Eng, and Operations.

Skills

DFT architecture
SoC design
MBIST
BISR
boundary-scan
analog/mixed-signal blocks
verification strategies
automation scripts
AI-assisted tooling

Education

Bachelor's degree
Master's degree
PhD

Tools

EDA tools

Job description

Cisco Systems, Inc. in California seeks a technical leader to define and productize high-performance mixed-signal ASICs and DFT frameworks.

You will own architecture for blocks and subsystems, partnering with domain experts to solve cross-functional challenges and lead scalable verification strategies across digital and analog domains. You will also drive reusable designs, automation flows, and engage with tool vendors and IP suppliers, collaborating with library, PnR, Test Eng, and Operations

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