ASIC/RTL Design Engineer

TPI Global Solutions; San Jose (CA); On-site; USD 130,000 - 195,000; Full time

Job summary

TPI Global Solutions seeks an experienced ASIC/RTL Design Engineer with strong RTL coding and hands-on analog design experience. You will develop RTL blocks in Verilog/SystemVerilog, simulate with VCS, and model analog/mixed-signal behavior, collaborating to deliver integrated ASIC solutions.

Responsibilities include design, debugging, testbench development, and optimization across digital and analog teams, using VCS, LTspice, and HSPICE.

Qualifications

• Experience in ASIC design and RTL coding.
• Proficiency in Verilog and/or SystemVerilog.
• Hands-on analog design or AMS modeling experience.
• Experience with Synopsys VCS, LTspice, and HSPICE.
• Strong digital logic knowledge and ASIC design methodologies.
• Ability to debug RTL and analog simulation issues.

Responsibilities

• Develop, implement, and maintain RTL code for ASIC and digital design blocks.
• Perform RTL design, simulation, and debugging for correctness and quality.
• Contribute to analog design and modeling activities and AMS interfaces.
• Use Synopsys VCS for RTL simulation and verification.
• Run analog simulations with LTspice and HSPICE.
• Collaborate with analog/digital teams to integrate RTL with mixed-signal blocks.
• Analyze results, identify issues, and troubleshoot at circuit level.
• Develop testbenches, models, and design documentation.
• Support verification, timing analysis, and optimization throughout ASIC development.

Skills

RTL coding

Verilog/SystemVerilog

Digital design

Analog modeling

Debugging RTL

Collaboration

Tools

Synopsys VCS

LTspice

HSPICE

Job description

We are seeking an experienced ASIC/RTL Design Engineer with strong RTL coding skills and hands-on experience in analog design and modeling. The ideal candidate will have a solid background in digital design, RTL development, and analog/mixed-signal modeling, along with experience using industry-standard simulation tools such as VCS, LTspice, and HSPICE.

Key Responsibilities:

• Develop, implement, and maintain RTL code for complex ASIC and digital design blocks using Verilog/SystemVerilog.
• Perform RTL design, logic development, simulation, and debugging to ensure functional correctness and design quality.
• Contribute to analog design and modeling activities, including analog circuit behavior modeling and analog/mixed-signal interface development.
• Use Synopsys VCS for RTL simulation, functional verification, and debugging.
• Perform analog circuit simulations and analysis using LTspice and HSPICE.
• Collaborate with analog and digital design engineers to integrate RTL components with analog and mixed-signal blocks.
• Analyze simulation results, identify design issues, and troubleshoot functional or circuit-level problems.
• Develop and maintain testbenches, simulation models, and design documentation.
• Support design verification, timing analysis, and design optimization throughout the ASIC development lifecycle.

Required Qualifications:

• Strong experience in ASIC design and RTL coding.
• Proficiency in Verilog and/or SystemVerilog.
• Hands-on experience with analog design, circuit modeling, or analog/mixed-signal design.
• Experience with Synopsys VCS, LTspice, and HSPICE simulation tools.
• Strong understanding of digital logic design, ASIC design methodologies, and simulation techniques.
• Experience debugging RTL and analog simulation issues.
• Ability to collaborate effectively with digital design, analog design, and verification teams.