Principal Mixed-Signal Design Verification Engineer

well-funded deeptech startup; New Hampshire; On-site; USD 120,000 - 160,000; Full time

Job summary

We are looking for a Principal Mixed-Signal Design Verification Engineer at a well-funded deeptech startup in New Hampshire. The role focuses on verifying and debugging Analog and Mixed Signal Integrated circuits used in Automotive and Industrial systems.

You will lead design verification for advanced sensor products, ensure quality with zero bugs, and mentor junior engineers. A BSEE or MSEE with over 10 years of experience is preferred.

Qualifications

• 10+ years of experience in analog/mixed signal IC design verification.
• Ability to clearly communicate ideas and concepts.
• Proven track record of leading a verification organization with zero bugs.

Responsibilities

• Support top level and block level verification of sensor ICs.
• Responsible for all aspects of design verification from initial plan to completed verification report.
• Generate object‑oriented System Verilog Testbenches for Analog IP verification.

Skills

Analog/Mixed-Signal Design Verification

System Verilog

Cadence tools

Scripting languages

Communication skills

Education

BSEE or MSEE

Tools

Cadence Design Tools

MathWorks MBD Tools

Job description

Principal Mixed-Signal Design Verification Engineer – Semiconductor organization

We are seeking Analog/Mixed‑Signal Design Verification Engineer to define process, verify and debug Analog and Mixed Signal Integrated circuits intended for Automotive and Industrial systems. In this role you will determine best modeling and simulation practices, including the use of behavioral models and object‑oriented test benches used to develop advanced sensors. Candidate should have strong technical and communication skills. You will be responsible for all product line verification, documentation and develop the verification tools and methodology of state‑of‑the‑art sensor products.

You will:

• Supporting top level and block level verification of sensor IC’s
• Responsible for all aspects of design verification from initial plan to completed verification report.
• Assist Systems/Design engineers in top‑down chip architecture development and feasibility.
• Generate object‑oriented System Verilog Testbenches for Analog IP verification
• Includes creation of Scoreboard, Sequencer, Driver, Monitor
• Creation class objects to allow for easier verification by other team members
• Translation of Jama based requirements to verification tests.
• Verification and documentation of ISO26262 Hardware Safety Requirements
• Assertion development to enforce analog and digital requirements.
• Regression testing
• Train engineers to read analog schematics and extract functionality for generation of models.
• Verify integrated circuit blocks such as amplifiers, comparators, precision front ends, oscillators, regulators, A/D and D/A converter models with their corresponding analog netlists.
• Generation of top‑level netlist for verification within the cadence mixed signal environment.
• Mentor junior level design and verification engineers
• Use various software environments for the behavioral modeling and verification of complex mixed‑signal integrated circuit systems.

Qualifications:

• BSEE, MSEE (preferred) with 10+ years of experience in analog/mixed signal IC design verification
• Ability to clearly communicate ideas and concepts.
• Proven track record of leading a verification organization with zero bugs.
• Proficient using Cadence design and Math works MBD tools.
• Use of scripting languages to facilitate the regression testing of designs.
• In depth understanding of System Verilog including RNM coding, creation of objects, virtual interfaces
• Sufficient understanding of analog/mixed signal design practices to allow for creation of logic, dc and timing accurate models.
• Able to solve challenging problems during verification and debug
• Experience modeling mixed signal blocks including bias networks, regulators, oscillators, bandgaps, filters, OTA’s, data converters.