Senior Mixed-Signal Modeling & Verification Engineer

Apple Inc.; Cupertino (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple Inc. in Cupertino seeks a seasoned digital mixed-signal modeling engineer to develop behavioral models and testbenches for wireless SoCs using SystemVerilog. You will work with a hands-on team across design and validation to ensure high-quality first silicon.

Responsibilities include building monitors, debugging testbenches, and scripting automation to accelerate verification. Preferred candidates hold a PhD or MS with 5+ years in analog/RF modeling and experience with SystemC or Python.

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Hands-on experience in Mixed-Signal Verification and Real Numbered Modeling.
• Knowledge of wireless technologies: WiFi, BT, UWB or radio systems.

Responsibilities

• Develop accurate and simulation‑efficient analog behavioral models for Analog/RF blocks in SystemVerilog.
• Build and reuse monitors, and checkers for RF, Mixed‑Signal and Digital blocks.
• Debug failures, fix testbench/model/checker issues, manage bug tracking, etc.
• Write scripts for automation of the flow and improve Mixed‑Signal verification methodology.
• Develop models that are emulation ready.

Skills

SystemVerilog

Mixed-Signal verification

Behavioral modeling

SystemC/C++

Python scripting

Debugging & testbench

Wireless knowledge

AMS knowledge

Education

BS in Electrical Engineering

MS/PhD in a relevant field

Tools

SystemC

Python tooling

MATLAB

Job description

Apple Inc. in Cupertino seeks a seasoned digital mixed-signal modeling engineer to develop behavioral models and testbenches for wireless SoCs using SystemVerilog. You will work with a hands-on team across design and validation to ensure high-quality first silicon.

Responsibilities include building monitors, debugging testbenches, and scripting automation to accelerate verification. Preferred candidates hold a PhD or MS with 5+ years in analog/RF modeling and experience with SystemC or Python.