Junior ASIC DFT Engineer - Design for Test & Automation

Cisco Systems, Inc.; San Jose (CA); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

Health insurance

Job summary

Cisco's Silicon One team is seeking an ASIC Design for Test Engineer focused on Design-for-Test. You will collaborate with frontend RTL and backend Physical Design to define DFT requirements early in the design cycle.

You will implement DFT features for ATE and in-system testing, create automation scripts, and work with Design, Verification, and Physical Design to validate test logic across all flows.

Qualifications

• A Bachelor's degree in ASIC DFT or related field within 3 years or expected within 12 months.
• Foundational understanding of JTAG, scan architectures, and BIST.
• Experience with EDA/ATPG tools and scripting in Python/Tcl/Perl.
• Gate-level simulations and debugging with VCS.

Responsibilities

• Implement DFT features for ATE, in-system test, debug, and diagnostics.
• Create and enhance automation scripts to improve robustness and efficiency.
• Collaborate with Design, Verification, and Physical Design to validate test logic.
• Validate test timing and logic equivalency using SystemVerilog.
• Utilize ATPG/EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for pattern generation and analysis.

Skills

SystemVerilog

JTAG protocols

Gate-level simulations

Python scripting

Tcl scripting

Perl scripting

VCS debugging

Education

Bachelor's degree in ASIC DFT or related field

Tools

TestMax

Tetramax

Tessent

PrimeTime

VCS

Job description

Cisco's Silicon One team is seeking an ASIC Design for Test Engineer focused on Design-for-Test. You will collaborate with frontend RTL and backend Physical Design to define DFT requirements early in the design cycle.

You will implement DFT features for ATE and in-system testing, create automation scripts, and work with Design, Verification, and Physical Design to validate test logic across all flows.