Junior ASIC DFT Engineer – AI Silicon Innovation

Cisco Systems, Inc; San Jose (CA); On-site; USD 130,000 - 190,000; Full time

Job summary

Cisco Systems, Inc in San Jose is seeking an ASIC Design for Test Engineer with a primary focus on Design-for-Test. You will work with frontend RTL teams, backend Physical Design teams to understand chip architecture and drive DFT requirements early in the design cycle.

Implement the Hardware Design-for-Test (DFT) features, create automation scripts to enhance robustness, and collaborate across teams to validate test timing and logic equivalence using SystemVerilog and ATPG tools.

Qualifications

• BS or higher in ASIC DFT or related field.
• Foundational knowledge of JTAG, scan architectures, and BIST.
• Basic exposure to scripting and EDA/ATPG tools.

Responsibilities

• Implement DFT features for ATE, in-system test, and diagnostics.
• Create and enhance automation scripts to improve robustness.
• Collaborate with frontend RTL and backend design teams to validate test logic.
• Validate test timing and logic equality using SystemVerilog and ATPG tools.
• Coordinate with design verification and physical design teams through post-silicon validation.

Skills

JTAG protocols

Scan architectures

BIST

Python scripting

Tcl scripting

Perl scripting

VCS debugging

Education

Bachelor's degree in ASIC/DFT or related field

Tools

TestMax

Tetramax

Tessent

PrimeTime

VCS

Job description

Cisco Systems, Inc in San Jose is seeking an ASIC Design for Test Engineer with a primary focus on Design-for-Test. You will work with frontend RTL teams, backend Physical Design teams to understand chip architecture and drive DFT requirements early in the design cycle.

Implement the Hardware Design-for-Test (DFT) features, create automation scripts to enhance robustness, and collaborate across teams to validate test timing and logic equivalence using SystemVerilog and ATPG tools.