DFT ASIC Engineer II: Design-for-Test in AI Silicon

Cisco Systems, Inc; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Cisco Systems, Inc. is seeking an ASIC Design for Test Engineer in the Silicon One group in California. The role focuses on design-for-test (DFT) for recent silicon, collaborating with frontend RTL, backend physical design, and verification teams to drive test requirements early in the design cycle.

You will implement DFT features for ATE and in-system test, develop automation scripts, validate test timing, and use ATPG/EDA tools to analyze patterns across the full silicon flow.

Qualifications

• Master's degree in ASIC Engineering or related field (0 years experience).
• Bachelor's degree with 2 years of work experience.
• Foundational understanding of JTAG, scan architectures, and BIST (memory BIST, boundary scan).
• Familiarity with EDA and ATPG tools; scripting in Python, Tcl, or Perl; gate-level simulations and VCS.

Responsibilities

• Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
• Create and enhance automation scripts to improve implementation robustness and efficiency.
• Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog.
• Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.

Skills

SystemVerilog

ATPG

Python

Tcl

Perl

VCS

Education

Master's degree in ASIC Engineering or related field

Bachelor's degree with 2 years of work experience

Tools

TestMax

Tetramax

Tessent

PrimeTime

Job description

Cisco Systems, Inc. is seeking an ASIC Design for Test Engineer in the Silicon One group in California. The role focuses on design-for-test (DFT) for recent silicon, collaborating with frontend RTL, backend physical design, and verification teams to drive test requirements early in the design cycle.

You will implement DFT features for ATE and in-system test, develop automation scripts, validate test timing, and use ATPG/EDA tools to analyze patterns across the full silicon flow.