Entry-Level ASIC DFT Engineer – Design-for-Test

Cisco; Allentown (Lehigh County); On-site; USD 95,000 - 157,000; Full time

Job summary

Cisco Systems is seeking an ASIC Design for Test Engineer to join the Silicon One team. You’ll drive design-for-test features and collaborate across RTL, physical design, and verification to ensure robust test solutions for next‑generation silicon.

Role emphasizes Python scripting, SystemVerilog validation, ATPG/EDA tool usage, and early DFT involvement in the design cycle. A strong foundation in JTAG and BIST is valued.

Qualifications

• Bachelor's degree in ASIC DFT or related field.
• Foundational understanding or exposure to JTAG, scan architectures, and BIST.
• Familiarity with EDA/ATPG tools and scripting (Python/Tcl/Perl).
• Experience with gate-level simulations and VCS debugging.
• Strong verification coursework including SystemVerilog and timing concepts.

Responsibilities

• Implement DFT features for ATE, in-system test, debug and diagnostics.
• Create and enhance automation scripts to improve robustness and efficiency.
• Collaborate with frontend RTL, backend PD, and verification teams to integrate test logic.
• Validate test timing and logical equivalency of designs using SystemVerilog.

Skills

ASIC DFT

JTAG familiarity

Python scripting

SystemVerilog

ATPG/EDA tools

Education

Bachelor's degree in ASIC/related field

Tools

TestMax

Tetramax

Tessent

PrimeTime

Job description

Cisco Systems is seeking an ASIC Design for Test Engineer to join the Silicon One team. You’ll drive design-for-test features and collaborate across RTL, physical design, and verification to ensure robust test solutions for next‑generation silicon.

Role emphasizes Python scripting, SystemVerilog validation, ATPG/EDA tool usage, and early DFT involvement in the design cycle. A strong foundation in JTAG and BIST is valued.