DFT Engineer – ASIC/SoC | Hybrid (San Jose)

Cisco Systems, Inc; San Jose (CA); Hybrid; USD 155,000 - 223,000; Full time

Benefits offered by this job

401(k) matching

Paid parental leave

Job summary

Cisco Systems, Inc. in San Jose, CA is seeking a Design-for-Testability (DFT) Engineer for a hybrid role performing three days per week from the office. You will drive DFT implementation, validation, and signoff for complex ASIC/SoC designs.

The ideal candidate has hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, and pattern validation, collaborating with RTL, verification, and test teams to ensure manufacturability and quality.

Qualifications

• Bachelor's degree and 5+ years related experience or higher.
• Experience with ASIC DFT implementation or validation.
• Familiarity with DFT tools like Tessent or DFT Compiler.

Responsibilities

• Support DFT implementation for ASIC/SoC blocks and subsystems.
• Implement and validate scan insertion, compression, OCC, MBIST, boundary scan.
• Run DFT rule checks and debug scan, clock, reset, and test-mode issues.
• Generate and validate ATPG patterns for fault models.
• Analyze test coverage and ATPG reports; debug issues.
• Develop Tcl/Python/Perl scripts to automate DFT flows.

Skills

ASIC DFT

DFT tools

ATPG

MBIST

OCC

Scripting (Tcl/Python/Perl/Shell)

Scan architecture

Education

Bachelor's degree in related field

Master's degree (preferred)

PhD (equivalent experience)

Tools

Siemens Tessent

Synopsys DFT Compiler/TestMAX

Job description

Cisco Systems, Inc. in San Jose, CA is seeking a Design-for-Testability (DFT) Engineer for a hybrid role performing three days per week from the office. You will drive DFT implementation, validation, and signoff for complex ASIC/SoC designs.

The ideal candidate has hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, and pattern validation, collaborating with RTL, verification, and test teams to ensure manufacturability and quality.