Hybrid Senior ASIC Design Engineer – Networking Chips

Hewlett Packard Enterprise; Durham (NC); Hybrid; USD 140,000 - 321,000; Full time

Benefits offered by this job

Hybrid work model

Career development programs

Job summary

Hewlett Packard Enterprise is seeking a highly motivated ASIC Design Engineer to join our Networking Silicon group in Durham, NC. You will architect complex modules for high-performance networking chips, write detailed specifications and implement designs in Verilog/SystemVerilog, with rigorous verification and collaboration with physical design for timing closure.

The role emphasizes mentoring junior engineers, leading technical efforts, and delivering power-aware, high-density silicon blocks

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering required.
• 7+ years of relevant ASIC design experience.
• Strong knowledge of Verilog/SystemVerilog and IC design processes.

Responsibilities

• Architect modules/subsystems for high-performance networking chips.
• Write detailed design specs, power/area/performance targets.
• Implement design using Verilog/SystemVerilog, verify with coverage.
• Collaborate with Physical Design for timing and floorplanning.
• Mentor new engineers and interns.

Skills

Verilog/SystemVerilog

ASIC Design

Power/Area/Performance

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree strongly desired

Tools

EDA tools

Job description

Hewlett Packard Enterprise is seeking a highly motivated ASIC Design Engineer to join our Networking Silicon group in Durham, NC. You will architect complex modules for high-performance networking chips, write detailed specifications and implement designs in Verilog/SystemVerilog, with rigorous verification and collaboration with physical design for timing closure.

The role emphasizes mentoring junior engineers, leading technical efforts, and delivering power-aware, high-density silicon blocks