Senior ASIC Design Engineer – Networking Silicon

Anysilicon; Roseville, Northern (CA, KY); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Senior ASIC Design Engineer to join its Networking Silicon group in Roseville, CA. This onsite role focuses on developing advanced networking chips for routers and switches in a fast-paced environment.

You will drive micro-architecture, collaborate across verification and physical design teams, and mentor junior engineers while delivering high-performance silicon.

Qualifications

• Bachelor’s degree in Electrical Engineering with 5+ years of relevant ASIC design experience.
• Strong analytical and problem-solving skills.
• Knowledge of computer architecture and networking protocols is a plus.
• Proficient coding skills in Verilog/SystemVerilog.
• Familiarity with synthesis, lint, and other EDA tools is desired.

Responsibilities

• Develop detailed micro-architecture specifications from functional specs meeting power/area targets.
• Write functional coverage and SystemVerilog Assertions (SVA) for verification.
• Collaborate with Physical Design for floorplanning and timing closure.
• Work with Verification to ensure full validation of design blocks.
• Mentor and provide guidance to new engineers and interns.

Skills

Verilog/SystemVerilog

Python/Perl

AI tooling experience

Education

Bachelor’s in Electrical Engineering

Master’s preferred

Tools

EDA tools

Synthesis

Job description

Hewlett Packard Enterprise is seeking a Senior ASIC Design Engineer to join its Networking Silicon group in Roseville, CA. This onsite role focuses on developing advanced networking chips for routers and switches in a fast-paced environment.

You will drive micro-architecture, collaborate across verification and physical design teams, and mentor junior engineers while delivering high-performance silicon.