Hybrid ASIC Verification Engineer for Networking SoCs

Hewlett Packard Enterprise; Durham (NC); Hybrid; USD 106,000 - 243,000; Full time

Job summary

Hewlett Packard Enterprise in Durham, NC seeks a highly motivated ASIC Verification Engineer to join our networking silicon development team. This hybrid role requires in-office presence 2 days per week and US citizenship preferred.

You will own block- or subsystem-level verification, develop advanced UVM environments, perform constrained random testing, debug complex designs, and collaborate with cross-functional teams to deliver high-quality ASIC/SoC.

Qualifications

• 4+ years of hands-on ASIC/SoC verification experience with test-plan ownership.
• Strong SystemVerilog and UVM expertise, including building verification environments from scratch.
• Experience with randomization, constraints, coverage analysis, and SVA assertions.

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Skills

4+ years ASIC/SoC verification

SystemVerilog

UVM

Randomization

Debugging SoC designs

Cadence Xcelium

Synopsys VCS

Mentor Questa

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise in Durham, NC seeks a highly motivated ASIC Verification Engineer to join our networking silicon development team. This hybrid role requires in-office presence 2 days per week and US citizenship preferred.

You will own block- or subsystem-level verification, develop advanced UVM environments, perform constrained random testing, debug complex designs, and collaborate with cross-functional teams to deliver high-quality ASIC/SoC.