Hybrid ASIC Verification Engineer - Clocking & SoC

Anysilicon; Santa Clara (CA); Hybrid; USD 110,000 - 180,000; Full time

Benefits offered by this job

Hybrid work

Job summary

NVIDIA’s Clocks team seeks an experienced ASIC Design Verification Engineer to improve clocking and reset logic verification for SOC and GPU products. You will drive test plans, automation, and validation flows using SystemVerilog, UVM, Python, and C++, coordinating closely with the clocks architecture and design groups.

The role emphasizes end-to-end verification from plan to production, requiring strong collaboration across time zones and with internal and external teams, to deliver bug-free

Qualifications

• BS or MS in Electrical Engineering or ECE or equivalent experience.
• 3+ years of proven design verification experience.
• Strong knowledge of logic design and architecture.
• Experience with SV, UVM, formal verification and coverage metrics.
• Exposure to block- and system-level verification.
• Proficient in SystemVerilog, Perl/Python and C++.
• Ability to collaborate across multiple groups and schedules.

Responsibilities

• Own validation of clocking structures in Tegra and GPU products end-to-end.
• Develop test plans, automation, validation flows and coverage metrics.
• Identify and fix bugs, ensuring clock designs are production-ready.
• Develop scalable verification solutions for complex problems across platforms.
• Utilize SV, UVM, C++, Perl and Python in verification tooling.
• Collaborate with clocks architecture and design teams for validation.
• Coordinate with internal and external teams across time zones.

Skills

SystemVerilog

UVM

C++

Python

Perl

Test plans

Pre-silicon verification

Collaboration

Education

BS in Electrical Engineering or Electrical and Computer Engineering

MS in Electrical Engineering or Electrical and Computer Engineering

Job description

NVIDIA’s Clocks team seeks an experienced ASIC Design Verification Engineer to improve clocking and reset logic verification for SOC and GPU products. You will drive test plans, automation, and validation flows using SystemVerilog, UVM, Python, and C++, coordinating closely with the clocks architecture and design groups.

The role emphasizes end-to-end verification from plan to production, requiring strong collaboration across time zones and with internal and external teams, to deliver bug-free