Senior ASIC Verification Engineer — Clocking & SoC Validation

NVIDIA; California (MO); On-site; USD 136,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA's Clocks Team is seeking a Senior ASIC Verification engineer with extensive experience in Design Verification to deliver high-quality clocking and reset logic across SOC and GPU ASICs. The role involves test plan development, automation, and validation for Tegra and GPU products, working with architecture and design teams and coordinating with teams across time zones.

Ideal candidates have 5+ years in verification, strong SystemVerilog/UVM/C++ skills, and the ability to drive pre-silicon

Qualifications

• BS or MS in EE/ECE or equivalent experience.
• 5+ years of relevant industry work experience.
• Good understanding of Logic Design and Architecture.
• Expertise in SV verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X-prop, etc.
• Exposure on block level and system-level verification.
• Strong coding skills in SystemVerilog, scripting languages (Perl/Python) and C++.
• Ability to collaborate and work with multiple groups.
• Prior experience in implementing Test plans for pre-silicon platforms.
• Understanding of DFT/IST is optional.

Responsibilities

• Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
• Tackle sophisticated problems and develop a scalable solution that works across platform.
• Hands on industry-standard verification tools and state of the art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
• Partnering closely with our clocks architecture and design team to validate our clocks design.
• Coordinate with internal and external teams across time zones.

Skills

SystemVerilog

UVM

C++

Python

Perl

Education

BS/MS in EE/ECE or equivalent

Tools

Formal Verification Tools

Coverage Tools

Profiling Tools

Job description

NVIDIA's Clocks Team is seeking a Senior ASIC Verification engineer with extensive experience in Design Verification to deliver high-quality clocking and reset logic across SOC and GPU ASICs. The role involves test plan development, automation, and validation for Tegra and GPU products, working with architecture and design teams and coordinating with teams across time zones.

Ideal candidates have 5+ years in verification, strong SystemVerilog/UVM/C++ skills, and the ability to drive pre-silicon