Senior ASIC Verification Engineer — High-Speed I/O, Equity

NVIDIA Corporation; Massachusetts; On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA seeks a Senior Design Verification Engineer to verify the design and implementation of High Speed I/O controllers for the world’s leading SOCs and GPUs. You will work in a dynamic, technology-focused company shaping products from consumer graphics to AI-driven systems.

In this role you will verify ASIC design with UVM, build reusable verification components, and collaborate across cross-functional teams to ensure robust, high-quality IP and interconnect implementations.

Qualifications

• Bachelor's or Master's degree (or equivalent experience) in a relevant field.
• 5+ years of design verification experience.
• Experience with IP or interconnect protocols such as Ethernet/USB/SATA.
• Proficient in SystemVerilog/UVM with strong debugging skills.

Responsibilities

• Verify ASIC design, architecture, and IP/sub-system level High Speed I/O controllers (Ethernet, NVLink) using UVM.
• Build reusable tests, monitors, and scoreboards with coverage-driven verification.
• Define verification scope, develop test plans and infrastructure; drive functional coverage.
• Collaborate with architects, designers, and silicon verification teams.

Skills

SystemVerilog

UVM

IP/interconnect verification

Random stimulus & coverage

Assertion-based verification

Debugging & analysis

Communication & collaboration

Education

Bachelor's or Master's Degree (or equivalent experience)

Job description

NVIDIA seeks a Senior Design Verification Engineer to verify the design and implementation of High Speed I/O controllers for the world’s leading SOCs and GPUs. You will work in a dynamic, technology-focused company shaping products from consumer graphics to AI-driven systems.

In this role you will verify ASIC design with UVM, build reusable verification components, and collaborate across cross-functional teams to ensure robust, high-quality IP and interconnect implementations.