ASIC Verification Engineer

Anysilicon; Santa Clara (CA); Hybrid; USD 110,000 - 180,000; Full time

Benefits offered by this job

Hybrid work

Job summary

NVIDIA’s Clocks team seeks an experienced ASIC Design Verification Engineer to improve clocking and reset logic verification for SOC and GPU products. You will drive test plans, automation, and validation flows using SystemVerilog, UVM, Python, and C++, coordinating closely with the clocks architecture and design groups.

The role emphasizes end-to-end verification from plan to production, requiring strong collaboration across time zones and with internal and external teams, to deliver bug-free

Qualifications

• BS or MS in Electrical Engineering or ECE or equivalent experience.
• 3+ years of proven design verification experience.
• Strong knowledge of logic design and architecture.
• Experience with SV, UVM, formal verification and coverage metrics.
• Exposure to block- and system-level verification.
• Proficient in SystemVerilog, Perl/Python and C++.
• Ability to collaborate across multiple groups and schedules.

Responsibilities

• Own validation of clocking structures in Tegra and GPU products end-to-end.
• Develop test plans, automation, validation flows and coverage metrics.
• Identify and fix bugs, ensuring clock designs are production-ready.
• Develop scalable verification solutions for complex problems across platforms.
• Utilize SV, UVM, C++, Perl and Python in verification tooling.
• Collaborate with clocks architecture and design teams for validation.
• Coordinate with internal and external teams across time zones.

Skills

SystemVerilog

UVM

C++

Python

Perl

Test plans

Pre-silicon verification

Collaboration

Education

BS in Electrical Engineering or Electrical and Computer Engineering

MS in Electrical Engineering or Electrical and Computer Engineering

Job description

NVIDIA, Santa Clara, CA 95051 Hybrid work

Job Description:

NVIDIA’s Clocks team is seeking an experienced ASIC Design Verification Engineer to enhance the quality of clocking and reset logic for SOC and GPU ASIC products. This role involves sophisticated verification processes to ensure bug-free designs that support a range of applications, including data centers, consumer graphics, self-driving cars, and artificial intelligence. The position requires innovative solutions to meet complex design specifications while balancing infrastructure constraints and testing speed.

Responsibilities:

• Own validation of clocking structures in Tegra and GPU products from start to finish.
• Develop test plans, automation, validation flows, coverage metrics, and execute tests.
• Identify and fix bugs, ensuring productization of clock designs.
• Develop scalable solutions for sophisticated problems across platforms.
• Utilize industry-standard tools and verification methodologies, including System Verilog, UVM, C++, Perl, and Python.
• Collaborate closely with the clocks architecture and design team for validation.
• Coordinate with internal and external teams across different time zones.

Qualifications:

• BS or MS in Electrical Engineering/Electrical and Computer Engineering or equivalent experience.
• 3+ years of proven design verification experience.
• Good understanding of logic design and architecture.
• Expertise in verification flows like SV constraint random verification, UVM, formal verification, and coverage metrics.
• Exposure to block-level and system-level verification.
• Strong coding skills in System Verilog, Perl/Python, and C++.
• Ability to collaborate with multiple groups.
• Prior experience in implementing test plans for pre-silicon platforms.

Skills:

• Experience automating tasks in the design verification process.
• Hands-on experience in object-oriented programming.
• Prior design or verification experience at the IP or block level.
• Experience developing methodologies used by others.
• Demonstrated ability to drive projects to completion.