Senior ASIC Verification Engineer - AI-Driven SoC & UVM

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking Senior Verification Engineers to ensure the integrity of leading SoCs and GPUs. You will verify ASIC designs, develop UVM testbenches, and collaborate across teams from IP to SoC levels.

Strong C/C++ skills and SVA are essential, with AI/LLM-driven workflow enhancements to speed coverage and debug. The role emphasizes deep IO knowledge (QSPI, UART, I2C, Ethernet), constrained random testing, and experience with Perforce and Makefiles.

Qualifications

• BS or equivalent in Electrical/Computer/CS; MS/PhD a plus
• 5+ years of ASIC verification experience at IP and SoC level
• Proven UVM testbenches from scratch and constrained random in production
• Strong C/C++ development for architectural golden models and HW/SW co-verification
• Deep knowledge of Low/High-Speed IOs (QSPI, UART, I2C, Ethernet) and AXI/APB
• Expert in SVA, code coverage, functional coverage and formal tests
• Strong debugging/analytical skills and methodical problem solving
• Proficient in Python, Perl, or TCL for automation

Responsibilities

• Verify ASIC SoCs and IPs to ensure first-pass silicon success
• Lead verification of ASIC design, architecture, golden models and micro-architecture using UVM
• Develop verification infrastructure and testbenches for complex logic
• Collaborate with architects, designers and pre/post-silicon teams for coverage
• Introduce AI/LLM-driven workflows to optimize testbench generation and debugging

Skills

ASIC verification

C/C++

UVM

SVA

Python scripting

Debugging

Constrained random testing

Education

BS in Electrical/Computer Engineering or CS

Tools

Perforce

Makefiles

Job description

NVIDIA Corporation is seeking Senior Verification Engineers to ensure the integrity of leading SoCs and GPUs. You will verify ASIC designs, develop UVM testbenches, and collaborate across teams from IP to SoC levels.

Strong C/C++ skills and SVA are essential, with AI/LLM-driven workflow enhancements to speed coverage and debug. The role emphasizes deep IO knowledge (QSPI, UART, I2C, Ethernet), constrained random testing, and experience with Perforce and Makefiles.