GPU ASIC Verification Engineer — High-Impact, Equity

NVIDIA; Durham (NC); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading GPUs and SoCs. You will verify ASIC design, architecture, golden models, and micro-architecture using advanced verification methodologies such as UVM, collaborating with architects and cross-functional teams.

The role emphasizes test bench development, debug tools, and strong SystemVerilog or HVL expertise, plus C/C++ programming.

Qualifications

• Bachelor's Degree in EE, CS or CE or equivalent experience.
• 2+ years of relevant experience.
• Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
• Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, GDB).
• Experience crafting test bench environments for unit and system level verification.
• Strong background in SystemVerilog or similar HVL.
• Expertise with C/C++ programming language.

Responsibilities

• Verify the design and implementation of the industry's leading GPUs.
• Verify the ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies such as UVM.
• Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Skills

SystemVerilog

C/C++

HVL

UVM

GDB

Education

Bachelor's Degree in EE/CS/CE or equivalent

Tools

VCS

Verdi

GDB

Job description

NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading GPUs and SoCs. You will verify ASIC design, architecture, golden models, and micro-architecture using advanced verification methodologies such as UVM, collaborating with architects and cross-functional teams.

The role emphasizes test bench development, debug tools, and strong SystemVerilog or HVL expertise, plus C/C++ programming.