Hybrid ASIC Verification Engineer (UVM/SystemVerilog)

NVIDIA Corporation; Austin (TX); Hybrid; USD 116,000 - 190,000; Full time

Job summary

NVIDIA in Austin, TX is seeking an ASIC Verification Engineer to verify our global IP across multiple product lines. You will partner with design and architecture teams to craft verification test plans, build RTL verification infrastructure, and drive coverage closure.

The role requires 2+ years of hands-on verification and expertise in SystemVerilog/UVM, Perl or Python. We offer a hybrid working model, competitive salary, equity, and benefits.

Qualifications

• BS/MS in Electrical or Computer Engineering (or equivalent).
• 2+ years in design verification with pre-silicon methods (UVM/SystemVerilog).
• Programming in Perl or Python; strong debugging and analysis skills.

Responsibilities

• Develop test plans, tests and verification infrastructure for global IP across multiple products.
• Define, develop, and automate verification flows and methodologies to efficiently build, deploy, and verify RTL.
• Ensure code and functional coverage of RTL which you will verify.
• Build verification components using SV/UVM methodology.
• Drive coverage-based verification closure and resolve issues with design teams.

Skills

SystemVerilog

UVM

Perl

Python

Debugging

Communication

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

dc_shell

VCS

Debussy

GDB

Job description

NVIDIA in Austin, TX is seeking an ASIC Verification Engineer to verify our global IP across multiple product lines. You will partner with design and architecture teams to craft verification test plans, build RTL verification infrastructure, and drive coverage closure.

The role requires 2+ years of hands-on verification and expertise in SystemVerilog/UVM, Perl or Python. We offer a hybrid working model, competitive salary, equity, and benefits.