Clocks ASIC Design Engineer – Hybrid + Equity

Nvidia Corporation in; Santa Clara (CA); Hybrid; USD 150,000 - 210,000; Full time

Benefits offered by this job

Hybrid work model

Equity

Job summary

NVIDIA is seeking an ASIC Design Engineer - Clocks IP (Finance) to architect clock domains for GPUs/CPUs and collaborate across teams from RTL to silicon bring-up in a hybrid environment in Santa Clara, CA. You will optimize PPA, participate in end-to-end ASIC cycles, and contribute to high-speed clocking solutions while leveraging Verilog and Python skills.

The role emphasizes experience in RTL design, verification, and timing, with competitive base salaries and equity, reflecting market norms

Qualifications

• BS in Electrical Engineering or equivalent (MS preferred).
• 2+ years of relevant work experience.
• Deep understanding of logic optimization techniques and PPA trade-offs.
• Excellent interpersonal skills and ability to collaborate with multiple teams.
• Experience in RTL design (Verilog), verification and logic synthesis.
• Strong coding skills in python or other industry-standard scripting languages.
• Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
• Implementing on-chip clocking networks is a bonus.

Responsibilities

• Architect the clock domain to satisfy functional, physical and testing design requirements.
• Engage with multiple teams and design GPU/CPU clocks to satisfy architectural, design and physical constraints.
• Improve Power, Performance, and Area (PPA) by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and timing closure in RTL clocking topologies.
• Collaborate with Physical design and timing teams to evaluate clocking concerns and develop solutions for high-speed clocking.
• Deliver clock RTL information to GPU, CPU and SOC verification timing and DFT teams.
• Involve end-to-end ASIC execution from micro-arch to silicon bringup.

Skills

Verilog RTL design

Python scripting

Logic optimization and PPA trade-offs

Collaboration / teamwork

Education

BS in Electrical Engineering (MS preferred)

Job description

NVIDIA is seeking an ASIC Design Engineer - Clocks IP (Finance) to architect clock domains for GPUs/CPUs and collaborate across teams from RTL to silicon bring-up in a hybrid environment in Santa Clara, CA. You will optimize PPA, participate in end-to-end ASIC cycles, and contribute to high-speed clocking solutions while leveraging Verilog and Python skills.

The role emphasizes experience in RTL design, verification, and timing, with competitive base salaries and equity, reflecting market norms