Senior ASIC Verification Engineer

NVIDIA; California (MO); On-site; USD 136,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA's Clocks Team is seeking a Senior ASIC Verification engineer with extensive experience in Design Verification to deliver high-quality clocking and reset logic across SOC and GPU ASICs. The role involves test plan development, automation, and validation for Tegra and GPU products, working with architecture and design teams and coordinating with teams across time zones.

Ideal candidates have 5+ years in verification, strong SystemVerilog/UVM/C++ skills, and the ability to drive pre-silicon

Qualifications

• BS or MS in EE/ECE or equivalent experience.
• 5+ years of relevant industry work experience.
• Good understanding of Logic Design and Architecture.
• Expertise in SV verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X-prop, etc.
• Exposure on block level and system-level verification.
• Strong coding skills in SystemVerilog, scripting languages (Perl/Python) and C++.
• Ability to collaborate and work with multiple groups.
• Prior experience in implementing Test plans for pre-silicon platforms.
• Understanding of DFT/IST is optional.

Responsibilities

• Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
• Tackle sophisticated problems and develop a scalable solution that works across platform.
• Hands on industry-standard verification tools and state of the art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
• Partnering closely with our clocks architecture and design team to validate our clocks design.
• Coordinate with internal and external teams across time zones.

Skills

SystemVerilog

UVM

C++

Python

Perl

Education

BS/MS in EE/ECE or equivalent

Tools

Formal Verification Tools

Coverage Tools

Profiling Tools

Job description

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC and GPU ASIC. The complexity of the clocks and resets design has increased many folds. This requires sophisticated verification to deliver a bug free clocks design to power our product lines ranging from Data Centers, Consumer graphics to Self-driving cars and the growing field of artificial intelligence. Modern clocking verification solutions need to be innovative, ensure quality in covering the complex design specifications and balance the constraints on infrastructure, re-usability, testing speed and multi-platform support.

What You'll Be Doing

• Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
• Tackle Sophisticated problems and develop a scalable solution that works across platform.
• Hands on industry-standard tools and state of the art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
• Partnering closely with our clocks architecture and design team to validate our clocks design.
• Coordinate with internal and external teams across time zones.

What We Need To See

• BS or MS in EE/ECE or equivalent experience.
• 5+ years of relevant industry work experience.
• Good understanding of Logic Design and Architecture.
• Expertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.
• Exposure on block level and system-level verification.
• Strong coding skills in System Verilog, scripting languages (Perl/python) and C++.
• Ability to collaborate and work with multiple groups.
• Prior experience in implementing Test plans for pre-silicon platforms.
• Understanding of DFT/IST is optional.

What to Stand Out From the Crowd: -

• Previous experience automating tasks in the design verification process
• Hands on experience in object-oriented programming
• Prior design or verification experience at the IP or block level
• Experience developing methodologies used by others
• Demonstrated ability to drive a project to completion

We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you are creative, curious, and motivated with real passion for technology, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 6, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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