HBM Core-Die Architect & Circuit Design Lead

Micron Technology, Inc.; Boise (ID); Sur place; USD 180 000 - 240 000; Plein temps

Avantages offerts par ce poste

Health insurance

Dental plan

Vision plan

Paid time off

Paid holidays

Résumé du poste

Micron Technology, Inc. in Boise, Idaho seeks an experienced HBM core‑die architect to own architecture definitions, circuit feasibility, and ARD development for next‑generation stacked memory products.

You will drive timing closure, reach high bandwidth with power/area efficiency, and collaborate across multiple teams to ensure design integrity from silicon bring‑up to release. The role requires strong DRAM architecture background, SPICE expertise, and a track record of cross‑functional

Qualifications

• Proven experience in DRAM architecture and circuit design (HBM, DDR, LPDDR, GDDR, or equivalent).
• Strong understanding of DRAM array architecture, row/column paths, sensing, datapath, refresh, and reliability mechanisms.
• Hands-on SPICE-based circuit simulation experience with HSPICE/Spectre/FineSim/PrimeSim.

Responsabilités

• Own HBM core‑die architecture including Bank/Bank‑Group organization, array partitioning, datapath, refresh, and reliability features.
• Drive critical DRAM circuit design and timing closure for row, column, sensing, and datapath paths.
• Develop and optimize architecture solutions for bandwidth, power, area, thermal, and reliability trade‑offs.
• Define and validate refresh, row‑hammer mitigation, data‑retention, and power‑efficient operation schemes.
• Lead architecture feasibility studies using transistor‑level simulation and physical implementation analysis.
• Collaborate with Array, Datapath, ECC, TSV, PDN, Layout, Verification, and DFT teams to drive end‑to‑end design execution.
• Support silicon bring‑up, characterization, failure analysis, and architecture‑to‑design handoff.

Connaissances

DRAM architecture

HBM/DDR family

SPICE simulation

Cross-functional work

Trade-off analysis

Communication skills

Outils

HSPICE

Spectre

FineSim

PrimeSim

Description du poste

Micron Technology, Inc. in Boise, Idaho seeks an experienced HBM core‑die architect to own architecture definitions, circuit feasibility, and ARD development for next‑generation stacked memory products.

You will drive timing closure, reach high bandwidth with power/area efficiency, and collaborate across multiple teams to ensure design integrity from silicon bring‑up to release. The role requires strong DRAM architecture background, SPICE expertise, and a track record of cross‑functional