HBM Core-Die Architect & Circuit Design Engineer

Micron Technology, Inc.; Folsom (CA); On-site; USD 139,000 - 308,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Paid time off

Paid holidays

Equity potential

Job summary

Micron Technology, Inc. is seeking an Engineer to own HBM core-die architecture and critical DRAM circuit design, impacting bandwidth, power, and reliability. You will drive architecture definition, circuit feasibility, and ARD development across advanced 3D-stacked HBM products for AI-enabled solutions.

The role requires hands-on DRAM experience, SPICE-based simulation, and collaboration with multiple teams to deliver end-to-end design execution and silicon bring-up support.

Qualifications

• Extensive DRAM architecture and circuit design experience.
• Hands-on SPICE-based circuit simulation experience.
• Ability to evaluate performance, power, area, thermal and reliability trade-offs.

Responsibilities

• Own HBM core-die architecture including Bank/Bank-Group organization and datapath.
• Drive circuit design and timing closure for row/column paths and sensing.
• Develop solutions for bandwidth, power, area, thermal and reliability trade-offs.
• Define refresh, row-hammer mitigation and power-efficient operation schemes.
• Lead feasibility studies using transistor-level simulation and physical analysis.
• Develop ARD with golden schematics, timing budgets and verification methods.
• Collaborate with Array, Datapath, ECC, TSV, PDN, Layout, Verification and DFT teams.
• Support silicon bring-up, characterization and architecture-to-design handoff.

Skills

DRAM architecture

HBM architecture

Circuit design

SPICE-based simulation

Cross-functional collaboration

Problem solving

Tools

HSPICE

Spectre

FineSim

PrimeSim

Job description

Micron Technology, Inc. is seeking an Engineer to own HBM core-die architecture and critical DRAM circuit design, impacting bandwidth, power, and reliability. You will drive architecture definition, circuit feasibility, and ARD development across advanced 3D-stacked HBM products for AI-enabled solutions.

The role requires hands-on DRAM experience, SPICE-based simulation, and collaboration with multiple teams to deliver end-to-end design execution and silicon bring-up support.