Senior DRAM Design Architect

Micron Memory Malaysia Sdn Bhd; Boise (ID); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology in Boise, Idaho is seeking a Principal Design Engineer for DRAM to lead memory circuit design from gate level to full chip implementations. You will collaborate with product engineering, test, process, and marketing to optimize power, speed, area, and reliability, using SPICE/Verilog, and contribute to AI-assisted design approaches.

The role demands strong background in semiconductor circuit design and proficiency with circuit simulation tools, with a focus on memory

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical field (or equivalent practical experience).
• Experience in semiconductor circuit design, layout, and optimization.
• Proficiency with circuit simulation and design tools such as SPICE and VERILOG.

Responsibilities

• Design and optimize memory circuits from gate-level to full chip implementations.
• Lead development of schematic blocks such as memory arrays, control logic, address decode, datapath, and internal test logic.
• Perform advanced circuit simulations using industry tools (e.g., SPICE, VERILOG) to validate performance.

Skills

Semiconductor circuit design

SPICE & Verilog

Circuit layout

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

SPICE

Verilog

Job description

Micron Technology in Boise, Idaho is seeking a Principal Design Engineer for DRAM to lead memory circuit design from gate level to full chip implementations. You will collaborate with product engineering, test, process, and marketing to optimize power, speed, area, and reliability, using SPICE/Verilog, and contribute to AI-assisted design approaches.

The role demands strong background in semiconductor circuit design and proficiency with circuit simulation tools, with a focus on memory