Senior Design Engineer, HBM & 3D-Stacked Memory

Micron Technology, Inc; Richardson (TX); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical/Dental/Vision

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. seeks a Sr Design Engineer to design, simulate, and validate next‑generation High‑Bandwidth Memory architectures and blocks.

You will collaborate with global teams to optimize manufacturing functions, cost, quality, and time‑to‑market across AI/HPC and graphics products. The role requires MS in CE or related field, 3+ years DRAM design/verification experience, and strong skills in HBM, high-speed I/O, PHY timing, and verification flow.

Qualifications

• Prior experience in HBM, DRAM, high‑speed I/O, or memory‑related designs.
• Familiarity with 3D stacked architectures and TSVs.
• Understanding of DRAM array control and high speed circuit design.
• Experience in function verification and timing analysis with mixed signal design.
• Familiar with device reliability and verification flow.
• Proficient with analog/digital simulation tools like HSPICE, VerilogHDL.

Responsibilities

• Design, optimize, and support post‑silicon bring‑up, failure analysis, and design correlation when required.
• Work closely with layout engineers on floorplanning, placement, routing, and design rule compliance.
• Review parasitics, EM/IR, and reliability results; drive design or layout fixes as needed.
• Ensure designs are manufacturable and meet foundry and packaging requirements.

Skills

HBM design

DRAM design

High-speed I/O

3D stacked tech

TSV signaling

PHY timing

Design verification

Analog/digital sim

VerilogHDL

HSPICE

Education

MS in Computer Engineering

Tools

HSPICE

VerilogHDL

PrimeSim

Job description

Micron Technology, Inc. seeks a Sr Design Engineer to design, simulate, and validate next‑generation High‑Bandwidth Memory architectures and blocks.

You will collaborate with global teams to optimize manufacturing functions, cost, quality, and time‑to‑market across AI/HPC and graphics products. The role requires MS in CE or related field, 3+ years DRAM design/verification experience, and strong skills in HBM, high-speed I/O, PHY timing, and verification flow.