ASIC Emulation Engineer — HW/SW Co-Verification Lead

Advanced Micro Devices; Santa Clara (CA); On-site; USD 160,000 - 230,000; Full time

Job summary

AMD in Santa Clara seeks a hands-on MTS ASIC Emulation Engineer to lead emulation of complex networking subsystems and SoCs using ZeBu, Veloce, and Palladium platforms. You will define emulation strategy, build scalable environments, and drive functional and performance validation before silicon.

The ideal candidate combines deep ASIC knowledge with strong emulation, debug, and software skills, capable of RTL handoff, workload enablement, regression, and verification closure while mentoring

Qualifications

• Hands-on ASIC emulation experience required.
• Experience with RTL, firmware, and software debugging.
• Strong C/C++, Python, Tcl, Shell scripting skills.
• Experience with emulation platforms such as ZeBu, Veloce, Palladium.

Responsibilities

• Define emulation strategy for complex networking IPs, subsystems, and SoCs.
• Bring up designs on ZeBu, Veloce, Palladium, or equivalents.
• Develop reusable emulation environments, transactors and infrastructure.
• Drive validation closure and performance verification before silicon.

Skills

ZeBu

Veloce

Palladium

RTL debugging

Firmware debugging

Software debugging

C/C++

Python

Tcl

Shell scripting

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science

Job description

AMD in Santa Clara seeks a hands-on MTS ASIC Emulation Engineer to lead emulation of complex networking subsystems and SoCs using ZeBu, Veloce, and Palladium platforms. You will define emulation strategy, build scalable environments, and drive functional and performance validation before silicon.

The ideal candidate combines deep ASIC knowledge with strong emulation, debug, and software skills, capable of RTL handoff, workload enablement, regression, and verification closure while mentoring