Senior ASIC DFT Engineer for High-Performance SoCs

Meta; Sunnyvale (CA); Hybrid; USD 180.000 - 240.000; Vollzeit

Zusammenfassung

Meta is seeking an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team. You will architect testability solutions for large-scale ASICs and drive DFT strategies from RTL to silicon bring-up.

Responsibilities include achieving high fault coverage across multiple fault models, supporting silicon bring-up and manufacturing test, and collaborating with design, physical implementation, and validation teams to deliver testable silicon at scale.

Qualifikationen

• Bachelor's degree in Computer Science, Computer Engineering, or related field.
• 6+ years of experience in DFT engineering for complex ASIC/SoC designs.
• Experience with scan insertion, ATPG, and MBIST implementations.

Aufgaben

• Architect and implement testability solutions for complex, high-performance ASICs.
• Define DFT strategies from RTL through silicon bring-up.
• Collaborate with design, physical implementation, and validation teams to ensure manufacturability and high fault coverage.

Kenntnisse

DFT engineering

ATPG pattern generation

MBIST implementation

scan insertion

ATE correlation

scripting

IEEE 1500

IEEE 1687 IJTAG

post-silicon failure analysis

yield improvement

SerDes test

chiplet designs

Ausbildung

Bachelor's degree in Computer Science or Computer Engineering

Tools

Tessent

Synopsys DFT Compiler

TetraMAX

Jobbeschreibung

Meta is seeking an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team. You will architect testability solutions for large-scale ASICs and drive DFT strategies from RTL to silicon bring-up.

Responsibilities include achieving high fault coverage across multiple fault models, supporting silicon bring-up and manufacturing test, and collaborating with design, physical implementation, and validation teams to deliver testable silicon at scale.