Design Verification Engineer (SystemVerilog/UVM) for ASICs

Apple, Inc.; Beaverton (OR); On-site; USD 120,000 - 180,000; Full time

Job summary

APPLE INC in Beaverton, Oregon is seeking a verification engineer to ensure SOC/IP quality. You will collaborate with design and micro-architecture teams, develop test plans and test benches, run regressions, triage bugs, and drive coverage to top results.

The role requires strong SystemVerilog/UVM experience, CRV or directed testing, C programming, and scripting in Python/Perl. Knowledge of Xcelium/Questa/VCS is essential.

Qualifications

• Master’s Degree in Computer Engineering, Electrical Engineering, or related field.
• Experience with SystemVerilog and UVM to write test bench code.
• CRV or directed testing to verify ASICs.
• C programming to write microprocessor tests for ASIC/Embedded tests.
• Reviewing design specs with design and micro-architecture teams.
• Developing test coverage plans and resolving gaps in ASIC test suites.
• Implementing IP block test environments and test cases for ASICs.
• Using Xcelium, Questa, or VCS for simulation failure analysis.
• Scripting in Python or Perl to automate test bench analysis.

Responsibilities

• Collaborate across disciplines to ensure the quality of SOC/IP.
• Review architecture specs and define verification methodology and test benches.
• Develop and execute test plans and coverage plans for ASICs.
• Run regressions, triage bugs, and analyze coverage to achieve top results.
• Communicate with design, architecture and software to cover use cases and corner cases.

Skills

SystemVerilog

UVM

CRV

Python

Perl

C programming

Education

Master’s degree in Computer/Electrical Engineering

Tools

Xcelium

Questa

VCS

Job description

APPLE INC in Beaverton, Oregon is seeking a verification engineer to ensure SOC/IP quality. You will collaborate with design and micro-architecture teams, develop test plans and test benches, run regressions, triage bugs, and drive coverage to top results.

The role requires strong SystemVerilog/UVM experience, CRV or directed testing, C programming, and scripting in Python/Perl. Knowledge of Xcelium/Questa/VCS is essential.