Design Verification

Apple, Inc.; Beaverton (OR); On-site; USD 120,000 - 180,000; Full time

Job summary

APPLE INC in Beaverton, Oregon is seeking a verification engineer to ensure SOC/IP quality. You will collaborate with design and micro-architecture teams, develop test plans and test benches, run regressions, triage bugs, and drive coverage to top results.

The role requires strong SystemVerilog/UVM experience, CRV or directed testing, C programming, and scripting in Python/Perl. Knowledge of Xcelium/Questa/VCS is essential.

Qualifications

• Master’s Degree in Computer Engineering, Electrical Engineering, or related field.
• Experience with SystemVerilog and UVM to write test bench code.
• CRV or directed testing to verify ASICs.
• C programming to write microprocessor tests for ASIC/Embedded tests.
• Reviewing design specs with design and micro-architecture teams.
• Developing test coverage plans and resolving gaps in ASIC test suites.
• Implementing IP block test environments and test cases for ASICs.
• Using Xcelium, Questa, or VCS for simulation failure analysis.
• Scripting in Python or Perl to automate test bench analysis.

Responsibilities

• Collaborate across disciplines to ensure the quality of SOC/IP.
• Review architecture specs and define verification methodology and test benches.
• Develop and execute test plans and coverage plans for ASICs.
• Run regressions, triage bugs, and analyze coverage to achieve top results.
• Communicate with design, architecture and software to cover use cases and corner cases.

Skills

SystemVerilog

UVM

CRV

Python

Perl

C programming

Education

Master’s degree in Computer/Electrical Engineering

Tools

Xcelium

Questa

VCS

Job description

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Beaverton, Oregon. Collaborating with all disciplines (vertical product model). Ensuring the quality of the SOC or an IP or subsystem. Reviewing design and architecture specifications and working closely with design & micro-architecture teams. Understanding the functional and performance goals of the design and use this knowledge to test effectively. Developing test plans, tests & coverage plans as well as define Apple’s next generation verification methodology & test benches. Communicating and collaborating with design, architecture and software to understand the use cases and corner conditions and driving test cases. Running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results. 40 hours/week.

Minimum Qualifications

• Master’s Degree or foreign equivalent in Computer Engineering, Electrical Engineering or related field.
• Experience and/or education must include:
• Utilizing System Verilog and UVM framework to write test bench code
• Creating test plans using constrained random verification (CRV) or directed testing to verify ASICs
• Utilizing C to write microprocessor tests for ASIC/Embedded tests.
• Reviewing design and architecture specifications and working closely with design and micro-architecture teams to understand functional and performance goals
• Developing test coverage plan, collecting test bench coverage, and resolving coverage gaps in ASIC test suite
• Implementing IP block test environments and test cases for ASICs
• Utilizing Xcelium, Questa, or VCS to analyze simulation failures
• Programming scripts in Python or Perl to automate test bench analysis

Preferred Qualifications

• N/A

This position is not subject to the application limits.

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