Design Verification Engineer — SoC IP & UVM Expert

Apple, Inc.; Melbourne (FL); On-site; USD 110,000 - 170,000; Full time

Job summary

Apple seeks an outstanding Design Verification Engineer to drive pre-silicon verification for IP designs. You will establish DV methodology, develop verification environments, and write tests to ensure bug-free first silicon across SoC/IP components.

You will create test plans, debug failures, and report DV progress using metrics such as bugs and coverage. Knowledge of UPF or scripting is a plus; LLM techniques will be used to improve efficiency and quality.

Qualifications

• BS degree in a technical subject area; minimum 3 years of relevant industry experience or equivalent.
• MS degree in a technical subject area strongly preferred.
• Strong knowledge of OOP, SystemVerilog and UVM.
• Experience with verification methodologies and tools such as simulators and DV environments.

Responsibilities

• Study design specification and create test plan.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to assist verification efficiently.

Skills

OOP

SystemVerilog

UVM

Education

BS degree in a technical subject area

MS degree preferred

Tools

Waveform viewer

Build and run automation

Coverage collection

Gate‑level simulations

Job description

Apple seeks an outstanding Design Verification Engineer to drive pre-silicon verification for IP designs. You will establish DV methodology, develop verification environments, and write tests to ensure bug-free first silicon across SoC/IP components.

You will create test plans, debug failures, and report DV progress using metrics such as bugs and coverage. Knowledge of UPF or scripting is a plus; LLM techniques will be used to improve efficiency and quality.