Senior SoC Verification Engineer - UVM & IP Integration

Apple, Inc.; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Job summary

Apple, Inc. in Austin is seeking a senior Design Verification Engineer to lead verification for cellular System-on-Chips.

You will craft reusable UVM test benches, build coverage-driven plans, and collaborate with multiple teams to ensure high-quality tape-out readiness across advanced cellular SoCs. Ideal candidates have 10+ years in verification, strong OO programming skills (Python/C++/Java/SystemVerilog), and hands-on experience with UVM-based environments and IP-level verification.

Qualifications

• B.S. degree in a technical field with 10+ years of experience
• Proficiency in object-oriented programming (Python, C++, Java, SystemVerilog)

Responsibilities

• Understand High-Efficiency SoC Architecture and peripherals (SPI, I2C, UART, DMA, DDR, PCIe, USB).
• Build coverage-driven verification plans from specifications.
• Create IP-level modules and sub-system verification TBs, sequences, and test infrastructure.
• Architect UVM-based test benches with multi-instance VIPs and SoC-level integration.
• Collaborate with DV methodology architects to improve verification flow.

Skills

Object-oriented programming

Python

C++

Java

Education

MS in EE/CS

Tools

UVM

SystemVerilog

Job description

Apple, Inc. in Austin is seeking a senior Design Verification Engineer to lead verification for cellular System-on-Chips.

You will craft reusable UVM test benches, build coverage-driven plans, and collaborate with multiple teams to ensure high-quality tape-out readiness across advanced cellular SoCs. Ideal candidates have 10+ years in verification, strong OO programming skills (Python/C++/Java/SystemVerilog), and hands-on experience with UVM-based environments and IP-level verification.