Senior Hardware DV Engineer (SystemVerilog/UVM)

Apple, Inc.; Cupertino (CA); On-site; USD 150,000 - 225,000; Full time

Job summary

Apple Inc. in Cupertino, California seeks a Senior Hardware Verification Engineer to verify complex chip designs and develop comprehensive test plans using SystemVerilog/UVM.

You will implement test benches in Verilog, create automated tests with Python, and collaborate across DV, design, and software teams to ensure robust silicon in a fast-paced environment. This role also offers base pay within the stated range with potential bonuses and relocation support.

Qualifications

• Bachelor’s degree in EE/CS or related field.
• Experience with Verilog testbenches and SystemVerilog/UVM.
• Proficiency in Python scripting for automation.
• Knowledge of ASIC/VLSI principles and timing/power considerations.

Responsibilities

• Collaborate with design and architecture to develop verification plans and features.
• Create, run and triage regressions of block, subsystem or chip-level simulations.
• Implement tests in SystemVerilog, Verilog, UVM and C per the test plan.
• Analyze coverage and update tests/constraints to close gaps.

Skills

Verilog

SystemVerilog

UVM

Python

C/C++

Digital Logic

ASIC/VLSI

Testbenches

Education

Bachelor's degree in Electrical Engineering and Computer Sciences, Electrical Engineering, Electronics Engineering or related field

Job description

Apple Inc. in Cupertino, California seeks a Senior Hardware Verification Engineer to verify complex chip designs and develop comprehensive test plans using SystemVerilog/UVM.

You will implement test benches in Verilog, create automated tests with Python, and collaborate across DV, design, and software teams to ensure robust silicon in a fast-paced environment. This role also offers base pay within the stated range with potential bonuses and relocation support.