Senior ASIC Verification Engineer - SystemVerilog/UVM

QUALCOMM, Inc.; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, CA is seeking a Verification Engineer for ASIC pre-silicon verification of power IPs.

You will develop testbenches with SystemVerilog/UVM, perform coverage, assertions, and formal verification, and automate verification flows to improve efficiency. You should have strong experience in SystemVerilog/Verilog, UVM, and C/C++, plus scripting skills in Python or Perl, with exposure to AMBA protocols and RTL concepts.

Qualifications

• Bachelor's degree in Engineering, Science, or related field.
• 2+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Responsibilities

• Perform pre-silicon test planning for digital power IPs.
• Develop testbenches using SystemVerilog/UVM and coverage.
• Create assertion models and formal verification (property checking).
• Learn and deploy UPF verification flow and automation to improve efficiency.

Skills

SystemVerilog

Verilog

C/C++

Python

Perl

UVM

Formal verification

Automation scripting

Object-oriented programming

Computer architecture

Education

Bachelor's degree in Engineering/Science

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

SystemVerilog/UVM

Verilog

VHDL

UVM

AMBA AXI/APB

Job description

Qualcomm Technologies, Inc. in San Diego, CA is seeking a Verification Engineer for ASIC pre-silicon verification of power IPs.

You will develop testbenches with SystemVerilog/UVM, perform coverage, assertions, and formal verification, and automate verification flows to improve efficiency. You should have strong experience in SystemVerilog/Verilog, UVM, and C/C++, plus scripting skills in Python or Perl, with exposure to AMBA protocols and RTL concepts.