Chip Package Designer – 2.5D/3.5D for ML HPCs

Google; Sunnyvale (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

Google Sunnyvale is seeking a Package Design Engineer to develop advanced 2.5D/3.5D package substrates for ML chips. You will work with SI/PI, thermal, mechanical, and PCB engineers to optimize electrical performance, reliability, and assembly across the design lifecycle.

You will manage routing feasibility, test vehicle creation, reviews, and documentation, driving advanced packaging technologies into production to improve PPA and reduce TCO.

Qualifications

• Bachelor's degree in Mechanical, Electrical, or related field or equivalent practical experience.
• 4 years of chip package substrate design experience using Cadence APD or Mentor Expedition.
• Experience in package substrate layout, design verification, DFM, and tape-out for production.
• Experience in design automation and scripting.

Responsibilities

• Manage physical package substrate design for large form-factor ML HPCs.
• Develop CAD flow and methodology for efficient substrate design.
• Drive co-design initiatives across chip/package/system levels with production sign-off.
• Collaborate with SI/PI, Thermal, Mechanical, and PCB teams to optimize designs.
• Define package substrate requirements and BOM, document processes.

Skills

Chip package design

Cadence APD

Mentor Expedition

Layout verification

DFM

Scripting

Education

Bachelor's degree in Engineering or related field

Tools

Cadence APD

Mentor Expedition

Job description

Google Sunnyvale is seeking a Package Design Engineer to develop advanced 2.5D/3.5D package substrates for ML chips. You will work with SI/PI, thermal, mechanical, and PCB engineers to optimize electrical performance, reliability, and assembly across the design lifecycle.

You will manage routing feasibility, test vehicle creation, reviews, and documentation, driving advanced packaging technologies into production to improve PPA and reduce TCO.