Senior IC Package Design Engineer - 2.5D/Interposer

TylSemi, Inc.; San Jose (CA); Hybrid; USD 180,000 - 216,000; Full time

Job summary

TYLsemi is seeking a Package Design Engineer to own design of IC packages (flip-chip, wirebond and 2.5D/interposer platforms) for high-speed digital and data-center-class products.

The successful candidate will drive package design from bump/ball map definition through substrate stack-up, routing, signal/power integrity closure, and tapeout — working closely with SI/PI, silicon design, and test engineering to deliver package designs that are robust against real silicon feedback.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.
• 5+ years of relevant IC package design experience.
• Experience with package-level SI/PI, thermal, and mechanical issues.

Responsibilities

• Own end-to-end package design in Cadence Allegro APD from feasibility through tapeout.
• Close high-speed signal nets using impedance control and length matching.
• Design and optimize PDN and power delivery networks for IC packages.
• Collaborate with SI/PI, silicon design, and test engineering.
• Drive DRC/DFM closure with substrate vendors and manage tapeout cycles.
• Coordinate with mechanical/thermal/reliability teams on warpage and underfill decisions.
• Document design decisions, stack-up specs, and via schedules.

Skills

Cadence APD

SIPI feedback

High-speed SI/PI

Education

Electrical/Electronics Engineering degree

Tools

Cadence Allegro

Cadence SKILL

Ansys IcePack

HFSS

Sigrity

Job description

TYLsemi is seeking a Package Design Engineer to own design of IC packages (flip-chip, wirebond and 2.5D/interposer platforms) for high-speed digital and data-center-class products.

The successful candidate will drive package design from bump/ball map definition through substrate stack-up, routing, signal/power integrity closure, and tapeout — working closely with SI/PI, silicon design, and test engineering to deliver package designs that are robust against real silicon feedback.