Senior 3D/2.5D Packaging Design Engineer

black.ai; Tempe (AZ); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Competitive salary

Early-stage equity opportunities

401(k) and other benefits

Health, dental, and vision coverage

Job summary

Syenta is seeking a Senior Advanced Packaging Design Engineer to lead physical layout and floor planning for 2.5D/3D interposers and high-density RDLs. You will drive die-to-package and package-to-board co-design, collaborating with ASIC, SI, and PI teams to ensure robust designs.

With 5+ years in semiconductor packaging, you will tackle design verification, DFM collaboration, and reliability optimization to push performance while managing manufacturability and thermal/structural challenges.

Qualifications

• BS/ MS in a technical discipline relevant to semiconductor packaging.
• 5+ years in semiconductor packaging layout, substrate design, or physical verification.

Responsibilities

• Physical Layout & Floor planning: lead the design, floor planning, pad/bump allocation, and complex routing of multi-layer organic substrates and 2.5D/3D interposer architectures.
• Co-Design Execution: drive die-to-package and package-to-board co-design with ASIC, SI, and PI teams.
• Design Verification: run and resolve DRC, LVS, and electrical rule checks for fine-pitch packaging tech.
• DFM & Manufacturing Collaboration: work with foundries/OSATs for DFM compliance and build-up sequences.
• Reliability Optimization: coordinate with thermal and mechanical teams to mitigate warpage, CTE mismatch, and thermo-mechanical stress.

Skills

Physical layout design

2.5D/3D IC integration

High-speed signal design

Power integrity

Cross-functional collaboration

Education

B.S. or M.S. in Electrical Engineering / Computer Engineering / Materials Science

Tools

Synopsys 3DIC Compiler

Cadence Allegro Package Designer Plus

Cadence Innovus

Siemens Xpedition Substrate Integrator

Calibre

Job description

Syenta is seeking a Senior Advanced Packaging Design Engineer to lead physical layout and floor planning for 2.5D/3D interposers and high-density RDLs. You will drive die-to-package and package-to-board co-design, collaborating with ASIC, SI, and PI teams to ensure robust designs.

With 5+ years in semiconductor packaging, you will tackle design verification, DFM collaboration, and reliability optimization to push performance while managing manufacturability and thermal/structural challenges.