ASIC Verification Engineer – Security & High Reliability

Amentum; Crane (IN); Presencial; USD 85 000 - 100 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Health insurance

401(k) matching

Paid time off

Educational reimbursement

Parental leave

Resumo da oferta

Amentum seeks a Computer Engineer to verify ASICs and/or FPGAs for high‑reliability, security‑focused systems for DoD customers. You will develop verification plans, build reusable SystemVerilog/UVM components, and automate EDA flows.

The role includes regression testing, debugging, and collaboration with RTL and integration teams to ensure robust designs. Minimum requirements include a degree in Computer or Electrical Engineering and experience with SystemVerilog and RTL concepts; DoD clearance

Qualificações

• Bachelor’s or graduate degree in Computer/Electrical Engineering.
• SystemVerilog and RTL concepts required/familiar.
• SVA or assertion-based verification beneficial.

Responsabilidades

• Verify ASICs/FPGA for high-reliability and security-focused apps.
• Develop verification plans based on design requirements.
• Build and maintain SystemVerilog/UVM testbenches and components.
• Create directed and constrained-random tests.
• Develop assertions, drivers, monitors, scoreboards, and coverage models.
• Run simulations/regression and debug failures.
• Review waveforms/logs/coverage to identify root causes.
• Collaborate with RTL/design teams; automate EDA flows and regressions.

Conhecimentos

SystemVerilog

VHDL familiarity

RTL concepts

SVA (SystemVerilog Assertions)

Python/Scripting

Formação académica

Bachelor’s or graduate degree in Computer or Electrical Engineering

Ferramentas

EDA tools (Siemens Cadence Synopsys)

SystemVerilog/UVM testbenches

Descrição da oferta de emprego

Amentum seeks a Computer Engineer to verify ASICs and/or FPGAs for high‑reliability, security‑focused systems for DoD customers. You will develop verification plans, build reusable SystemVerilog/UVM components, and automate EDA flows.

The role includes regression testing, debugging, and collaboration with RTL and integration teams to ensure robust designs. Minimum requirements include a degree in Computer or Electrical Engineering and experience with SystemVerilog and RTL concepts; DoD clearance