A leading technology company in San Jose is seeking an experienced ASIC Verification Engineer to develop and verify cutting-edge SoCs. The ideal candidate should have at least 10 years in ASIC verification, a Bachelor's degree in a relevant field, and expertise in System Verilog and UVM methodology. Join a diverse team working on innovative solutions in a dynamic environment.
Qualifications
10+ years of relevant experience in ASIC verification field.
Intimate knowledge of UVM methodology.
Experience with code coverage and formal verification tools.
Responsibilities
Developing System Verilog/UVM based communication protocol components.
Supporting HW/SW bring-up and debug.
Cooperating with system engineers to solve technical issues.
Education
Bachelor's degree in CS/EE
Master's degree desired
Tools
System Verilog
Python
Perl
UVM methodology
Job description
Overview
We are seeking an ASIC Verification Engineer with a solid ASIC/FPGA verification test strategy & development and debugging skills.
Qualifications
Masters degree desired, Bachelor's degree in CS/EE is required.
10+ years of relevant experience in ASIC verification field.
Should have worked on developing/implementing test plans at the chip-level for complex ASICs.
Fluent in System Verilog and scripting languages such as Python or Perl.
Must have intimate knowledge of UVM methodology.
Knowledgeable about assertions and functional coverage
Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
Very good communication skills and ability and desire to work in a geographically diverse team environment.
Familiarity with embedded processor & bus functional protocols would be bonus
Familiarity with external memory interface protocols would be a bonus
Familiarity with validation experience with any emulation platforms would be a bonus
Responsibilities
Working as independent contributor in development and verification of the world leading SoCs based on latest technology ASICs and FPGAs
Developing System Verilog/UVM based communication protocol components
Working on test plan based on functional requirements as well as applicable standards requirements
Working with experts of different areas to ensure the most competitive solutions
Cooperating with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues