Design Verification Engineer (Semiconductor / ASIC / VLSI)

Emonics LLC; Chicago (IL); On-site; USD 80,000 - 120,000; Full time

Job summary

A semiconductor design company based in Chicago is seeking a Design Verification Engineer to ensure the functional correctness and reliability of complex semiconductor designs. Responsibilities include developing verification plans, building verification environments using SystemVerilog/UVM, and performing RTL debugging. The ideal candidate holds a relevant degree and has strong digital design understanding, UVM experience, and familiarity with simulation tools. This role plays a critical part in ensuring product readiness and quality before tape-out.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering or related field.
• Strong understanding of digital design and computer architecture.
• Hands-on experience with UVM.

Responsibilities

• Develop and execute functional verification plans for ASIC/SoC designs.
• Build SystemVerilog/UVM-based verification environments.
• Write and maintain testbenches, test cases, assertions, and coverage models.
• Perform RTL debugging and collaborate with design engineers.
• Ensure verification completeness using functional and code coverage metrics.

Skills

Digital design understanding

Computer architecture knowledge

UVM experience

Simulation tools experience (VCS, Questa, Xcelium)

Functional coverage and assertions knowledge

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

VCS

Questa

Xcelium

Job description

We are seeking a Design Verification Engineer to ensure the functional correctness, performance, and reliability of complex semiconductor designs such as ASICs, SoCs, GPUs, or CPUs. The role focuses on developing robust verification environments and validating RTL designs prior to tape-out.

Key Responsibilities

• Develop and execute functional verification plans for ASIC/SoC designs
• Build SystemVerilog/UVM-based verification environments
• Write and maintain testbenches, test cases, assertions, and coverage models
• Perform RTL debugging and work closely with design engineers to resolve issues
• Ensure verification completeness using functional and code coverage metrics
• Participate in design reviews, spec reviews, and tape-out readiness
• Support regression testing and automation
• Contribute to continuous improvement of verification methodologies and flows

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or related field
• Strong understanding of digital design and computer architecture
• Hands-on experience with:
  • UVM (Universal Verification Methodology)
• Experience with simulation and debugging tools (VCS, Questa, Xcelium)
• Knowledge of functional coverage, assertions, and constrained random testing

Common Job Title Variations

• ASIC Verification Engineer
• VLSI Verification Engineer
• SoC Verification Engineer
• Hardware Verification Engineer