Senior Hardware Security Verification Architect

1010 Analog Devices Inc.; Wilmington (MA); On-site; USD 110,000 - 152,000; Full time

Benefits offered by this job

Discretionary bonus

Medical, vision and dental coverage

401k

Paid vacation/holidays/sick time

Job summary

Analog Devices, Inc. is seeking a Senior Design Verification Engineer for its Security IP team to own verification across complex security IP and subsystems.

You will develop advanced verification environments, drive coverage closure, debug failures, and contribute reusable methodologies while collaborating with RTL, firmware, and security experts. The role requires SystemVerilog/UVM expertise, constrained-random testing, and SoC verification experience in Linux environments, with exposure to

Qualifications

• Degree in Electrical/Computer Engineering or related field.
• 4–7 years of digital design verification experience.
• Proficiency with SystemVerilog/UVM and verification concepts.

Responsibilities

• Own block- and subsystem-level verification for security IPs and enclaves.
• Develop verification plans from architecture specs and threat models.
• Create, extend, and maintain SystemVerilog/UVM environments and scoreboards.
• Develop constrained-random and directed test scenarios for security behavior.
• Drive coverage closure via code/functional/coverage analysis and regression.

Skills

SystemVerilog/UVM

Constrained-random verification

Functional coverage

SVA/Assertion-based verification

RTL simulation & debug tools

Python/Perl/Tcl scripting

SoC verification with C tests

Linux experience

ARM Cortex-M / RISC-V experience

APB/AHB/AXI/QSPI/UART/DMA interfaces

Education

Bachelor's or Master's degree in Electrical Engineering / Computer Engineering / Computer Science

Tools

VCS

Xcelium

Simvision

Verdi

Questa

Job description

Analog Devices, Inc. is seeking a Senior Design Verification Engineer for its Security IP team to own verification across complex security IP and subsystems.

You will develop advanced verification environments, drive coverage closure, debug failures, and contribute reusable methodologies while collaborating with RTL, firmware, and security experts. The role requires SystemVerilog/UVM expertise, constrained-random testing, and SoC verification experience in Linux environments, with exposure to