ASIC Verification Engineer - Security-Focused (UVM/SV)

Amentum

Texas

Presencial

USD 85 000 - 100 000

Tempo integral

Há 5 dias
Torna-te num dos primeiros candidatos

Uma candidatura completa num minuto

Currículo e carta de apresentação personalizados, prontos a enviar.

Ultrapassa os filtros ATS

Vantagens oferecidas por esta oferta de emprego

Health insurance
Dental insurance
Vision insurance
Paid time off
401(k) matching
Educational reimbursement
Parental leave
Employee stock purchase plan
Tax-saving options
Disability insurance
Life insurance
Pet insurance

Resumo da oferta

Amentum is seeking a Computer Engineer to verify ASICs and/or FPGAs for high-reliability, security-focused systems supporting Department of War customers.

The engineer will develop verification plans, build SystemVerilog/UVM testbenches, create directed and constrained-random tests, and develop assertions and coverage models. Collaboration with RTL/design teams and automation of EDA flows are required.

Qualificações

  • Bachelor's or graduate degree in Computer Engineering or Electrical Engineering required.
  • Experience with SystemVerilog and RTL concepts expected.
  • Familiarity with directed/random verification and SVA.
  • Knowledge of testbench development and coverage concepts.

Responsabilidades

  • Verify ASICs and/or FPGAs for high-reliability and security-focused applications.
  • Develop verification plans based on design requirements and architecture docs.
  • Build and maintain SystemVerilog/UVM testbenches and reusable components.
  • Create directed and constrained-random tests to validate functionality and edge cases.
  • Develop assertions, drivers, monitors, scoreboards, and coverage models.
  • Execute simulations and regression test suites; analyze failures and root causes.
  • Collaborate with RTL design and other teams to resolve issues.
  • Automate EDA flows and regression reporting via scripting.
  • Document verification results, defects, and test status.

Conhecimentos

SystemVerilog
VHDL
Digital design
RTL concepts
Directed & constrained random
SystemVerilog Assertions (SVA)
Code/functional coverage
Waveform debugging
Python scripting
UART/SPI/I2C/MIPI/LVDS/DMA
EDA tools
ASIC verification flow
DoD Secret Clearance

Formação académica

Bachelor's or graduate degree in Computer or Electrical Engineering

Ferramentas

EDA tools (Siemens Cadence Synopsys)

Descrição da oferta de emprego

Amentum is seeking a Computer Engineer to verify ASICs and/or FPGAs for high-reliability, security-focused systems supporting Department of War customers.

The engineer will develop verification plans, build SystemVerilog/UVM testbenches, create directed and constrained-random tests, and develop assertions and coverage models. Collaboration with RTL/design teams and automation of EDA flows are required.

Obtém a tua avaliação gratuita e confidencial do currículo.

ou arrasta e larga o ficheiro aqui.

Similar jobs

Ofertas semelhantes que vale a pena comparar

ASIC Verification Engineer – Security & High Reliability
ASIC Verification Engineer – Security & High Reliability

Amentum • Crane (IN)

Presencial
USD 85 000 - 100 000
Health insurance
401(k) matching
Paid time off
+2
ASIC Verification Engineer
ASIC Verification Engineer

Amentum • Texas

Presencial
USD 85 000 - 100 000
Health insurance
Dental insurance
Vision insurance
+9
Verification Engineer, SoC/ASIC | UVM & SystemVerilog
Verification Engineer, SoC/ASIC | UVM & SystemVerilog

Efficient Computer • San Francisco (CA), Pittsburgh, Austin (TX)

Presencial
USD 130 000 - 180 000
10% annual bonus
Equity
401(k) match
+3
Verification Engineer: SV/UVM for SoC/AI Projects
Verification Engineer: SV/UVM for SoC/AI Projects

Omnicom Production • Toponas (CO)

Presencial
USD 90 000 - 140 000
Staff ASIC Verification Architect (SoC/IP) – UVM Expert
Staff ASIC Verification Architect (SoC/IP) – UVM Expert

Meta • Sunnyvale (CA)

Presencial
USD 178 000 - 250 000
Bonus
Equity
Benefits
Junior ASIC Verification Engineer (SV/UVM)
Junior ASIC Verification Engineer (SV/UVM)

Cisco Systems, Inc. • San Jose (CA)

Presencial
USD 100 000 - 165 000
Principal Engineer - ASIC Verification
Principal Engineer - ASIC Verification

Nokia • San Jose (CA)

Presencial
USD 130 000 - 160 000
Senior FPGA/ASIC Verification Engineer — SystemVerilog/UVM
Senior FPGA/ASIC Verification Engineer — SystemVerilog/UVM

MissionHires • City of Rochester (NY)

Presencial
USD 100 000 - 130 000
Senior ASIC Verification Engineer - UVM & SystemVerilog
Senior ASIC Verification Engineer - UVM & SystemVerilog

Mogi I/O : OTT/Podcast/Short Video Apps for you • Bastrop (TX)

Presencial
USD 160 000 - 180 000
ASIC Verification Engineer
ASIC Verification Engineer

Amentum • Crane (IN)

Presencial
USD 85 000 - 100 000
Health insurance
401(k) matching
Paid time off
+2